The present invention relates to digital audio decoding. More specifically, the invention relates to hardware cores for decoding audio data encoded according to the MPEG-1 standard, MPEG-2 standard or AC-3 standard.
Various standards have been developed for the purpose of providing digitally encoded audio data that can be reconstructed to provide good quality audio playback. In the late 1980s, a digital audio/video reconstruction standard known as "MPEG" (for Motion Pictures Experts Group) was promulgated by the International Standards Organization (ISO). MPEG syntax provides an efficient way to represent audio and video sequences in the form of compact coded data. MPEG unambiguously defines the form of a compressed bit stream generated for digital audio/video data. Given the knowledge of the MPEG rules, one can thus create a decoder which reconstructs an audio/video sequence from the compressed bit stream.
MPEG-2 was initiated in the early 1990s to define a syntax for higher quality audio playback for broadcast video. The MPEG-1 audio standard is described in a document entitled "Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 MBit/s" (Part 3 Audio) 3-11171 rev 1 (1995) (hereinafter "the MPEG-1 Document"). The MPEG-2 audio standard is described in a document entitled "Generic Coding of Moving Pictures and Associated Audio Information" ISO/IEC 13818-3 (1994) (hereinafter "the MPEG-2 Document"). Both standards documents are incorporated herein by reference for all purposes. Both documents are available from ISO/IEC Case Postale 56, CH-1211, Geneva 20, Switzerland.
A competing standard employing Dolby processing and known as "AC-3" has also been developed by the United States Advanced Television Systems Committee for digital encoding and decoding of audio data. This standard is described in the "Digital Audio Compression (AC-3)" draft ATSC STANDARD" AC3STD68.DOC (1994) (hereinafter "the AC-3 Document") which is available from Dolby Laboratories, Inc. located in San Francisco, Calif. and is incorporated herein by reference for all purposes.
The MPEG-2 audio decoding algorithm requires certain steps such as decoding of bit allocation, decoding of scale factors, variable length decoding of audio samples, requantization of samples, inverse discrete cosine transform matrixing, and windowing. The AC-3 audio decoding algorithm requires certain steps such as bit allocation, dequantization, decoupling, rematrixing, dynamic range compression, inverse fast fourier transform, and windowing and de-interleaving.
While CPU digital processing power has improved markedly in recent years, the sheer volume of encoded audio/video data that must be rapidly decompressed and played back generally requires some dedicated system hardware, beyond the CPU, for MPEG-2 decoding. CPUs like SPARC from Sun Microsystems, Inc. of Mountain View, Calif., MIPS from Silicon Graphics, Inc. of Mountain View, Calif., Pentium from Intel Corporation of Santa Clara, Calif., etc. cannot, in themselves, handle multi-channel MPEG-2 audio decoding simultaneously with video decoding, at a low system clock. Thus, software/firmware implementation of the MPEG-2 decoding algorithms is not yet practical for mass market consumer applications, and dedicated hardware must be employed to perform at least some MPEG-2 decoding functions.
While the ISO/MPEG-2 and AC-3 standards do specify the form that encoded audio data must take, they do not specify either the exact sequence of steps or the hardware that must be employed in decoding the data. Thus, designers of MPEG-2 and AC-3 decoding systems are free to provide their own designs for particular applications. In fact, it is expected that each time an MPEG-2 or AC-3 decoder is to be designed for a new application, a designer will generate a new integrated circuit layout for the decoder.
Various MPEG-2 decoder chips are now available including the HDM8211M (from Hyundai Corporation of Seoul Korea) full MPEG-2 decoder of audio, video, and system (transport) bitstreams. See Bursky, "Single Chip Performs Both Audio and Video Decoding" Electronic Design, Apr. 3, 1995, pp. 77-80. Similarly, various AC-3 decoder chips are now available including the ZR38500 six channel Dolby digital surround processor (from Zoran Corporation of Santa Clara, Calif.).
Additionally, representative chips for decoding both MPEG and AC-3 encoded data include the ZR38521 two channel Dolby AC-3 and two channel MPEG-1 decoder and ZR38600 programmable Dolby AC-3 and MPEG-2 audio processor, all available from Zoran Corporation of Santa Clara, Calif. Other such representative chips include a Six Channel Decoder IC available from SGS Thompson of Grenoble, France and Thompson Multimedia of Hannover, Germany and a Common Transform Engine for MPEG/AC-3 audio decoding available from Motorola Semiconductor of Phoenix, Ariz.
None of these products shares resources for decoding both AC-3 and MPEG-l/MPEG-2 encoded data. Typically they employ a digital signal processing (DSP) core, which is normally loaded onto an on-chip ROM and has microprogrammed thereon logic instructions for AC-3 decoding that are totally separate from the logic instructions for MPEG decoding. Thus, it would be desirable to have a system optimized for decoding both of these formats.